1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device including a timing controller with the decreased number of pins.
2. Discussion of the Related Art
With the recent development of information technology (IT), a flat display device has attracted great attention as the visual information communication medium. For strengthening the competitiveness, it is important for the flat display device to realize various advantages such as low power consumption, thin profile, lightness in weight, and high picture quality.
A typical example of the flat display device, liquid crystal display (LCD) device, displays an image by the use of optical anisotropy of liquid crystal. The LCD device has advantages of thin profile, small size, low power consumption, and high picture quality.
The LCD device individually supplies video information to respective pixels arranged in a matrix configuration, whereby light transmittance of the pixels are adjusted and thus desired image is displayed thereon. Thus, the LCD device includes a liquid crystal display panel in which the pixels serving as the minimum unit for displaying the image are arranged in the active matrix configuration; and a driver for driving the liquid crystal display panel. Also, since the LCD device cannot emit light in itself, the LCD device necessarily requires a backlight unit for supplying the light. The driver includes a timing controller, a gate driver, and a data driver.
FIG. 1 is an exemplary view illustrating a pin connection structure between a timing controller and a source drive IC in a related art LCD device. FIG. 2 is an exemplary view illustrating a waveform in a control signal and a video signal outputted from a timing controller in a related art LCD device.
The related art LCD device includes a timing controller 14, a gate driver (not shown), a data driver (not shown), and a liquid crystal display panel (not shown). The timing controller 14 outputs a gate control signal and a data control signal for respectively controlling gate and data drivers; and samples and rearranges digital video data (RGB); and outputs the sampled and rearranged data. The gate driver supplies a scan pulse to each gate line of the liquid crystal display panel in response to the gate control signal. The data driver supplies a pixel signal to each data line of the liquid crystal display panel in response to the data control signal. The liquid crystal display panel includes a plurality of liquid crystal cells driven by the scan pulse and pixel signal, to thereby display image. At this time, the data driver includes a plurality of source drive ICs (or data drive ICs) 17.
The timing controller 14 outputs the gate control signal for controlling the gate driver and the data control signal controlling the data driver by the use of vertical/horizontal synchronous signals and clock signals supplied from a system. Also, the timing controller 14 samples and rearranges the digital video data (video signal, RGB) transmitted from the system, and then supplies the sampled and rearranged video data to the data driver.
The data driver includes a plurality of source drive ICs 17 for receiving the video signal from the timing controller 14, and driving the data line of the liquid crystal display panel.
In the related art LCD device, the timing controller (T-Con) 14 separates the video signal of mini-LVDS and control signal from each other, and supplies the separated signals to the source drive IC 17, thereby causing the increased number of pins in the timing controller 14.
In the timing controller 14, as shown in FIG. 1, there are 14 pins for transmitting the video signal (mini-LVDS) to the source drive IC (FHD reference), and 5 pins for transmitting the control signal (SOE, POL, POL2, CSC, H2, and etc.) to the source drive IC. Thus, the video signal and control signal outputted from the timing controller 14 have different 19 waveforms, as shown in FIG. 2.
Also, since the source drive IC 17 receives the separated video signal and control signal, the source drive IC 17 requires the pins whose number is the same as those of the timing controller 14.
That is, in case of the related art LCD device, the video signal and control signal are received and transmitted while being separated from each other, whereby each of the timing controller 14 and source drive IC 17 requires 19 pins. Thus, the timing controller 14 and source drive IC 17 are increased in size.
In the related art LCD device, the video signal and control signal are transmitted via the large-numbered pins and lines formed between the timing controller 14 and source drive IC 17, which might cause the increased loss of pin and package.